My two cents about 1) ... NAND flash memory has indeed a limited number of program/erase cycles, but
The same flash (depending on manufacturer) and/or the filesystem which manages it, can have built-in mechanisms to detect and correct single-double (or even more) bit errors per page, which can be due to defects or cells that have been written/erased many times and become defective.
There are also mechanisms to mark bad blocks, which are a small % of the total, so that the user will not worry about it.
Also, most filesystems suitable for NAND (yaffs2, ext-4) take control (also depending on implementation) of which pages have been written in order to improve overall flash life.
Buffering and other strategies are also part of these file systems, which result in faster operations while optimizing flash access.
So only if you design an embedded system and have an unmanaged NAND chip, you would have to worry about which pages have been written more often, care for error correction/detection techniques and so on...